For example, as one of techniques of increasing a downlink communication speed, DC-HSDPA (Dual Cell-High Speed Downlink Packet Access) which is standardized by the 3GPP (Third Generation Partnership Project) which is an organization for standardization of manufactures is proposed. The DC-HSDPA is a technique of performing high-speed communication utilizing a communication system called HSPA (High Speed Packet Access). In the DC-HSDPA, two adjacent frequency bands (carriers) are simultaneously received using one terminal to double the transmission speed. Therefore, in a communication system adopting the DC-HSDPA, a terminal separates a received DC-HSDPA-based signal into signals having respective frequency bands by a predetermined method and performs a demodulating process on each of the frequency bands so separated.
As a predetermined method of separating such a DC-HSDPA-based signal as mentioned above using a terminal, for example, a method of receiving the DC-HSDPA-based signal using a single analog circuit, converting the signal into a digital signal and separating the A/D converted digital signal by digital signal processing is proposed. Specifically, first, the analog circuit performs a receiving process in a frequency band of 10 MHz and then converts the received analog signal to the digital signal. Then, a digital circuit separates the digital signal for two channels into respective signals by digital signal processing. For example, a frequency shift circuit which is disposed for each channel shifts (±2.5 MHz) the central frequency of the digital signal (10 MHz) for two channels and then a digital filter for each channel extracts only a desired frequency band (5 MHz) from the signal. Owing to execution of processing as mentioned above, it may become possible to separate the digital signal for two channels into channel-based signals.
Next, an existing frequency shift circuit which is used to separate a digital signal for two channels as mentioned above into channel-based signals will be described. For example, the existing frequency shift circuit generates a rotor ω which is a phase rotation amount by loop operation using a complex multiplier that inputs a complex exponential signal exp(j2πf t) wherein t denotes a sampling period and a rotor in a previous sampling period. Then, the existing frequency shift circuit shifts the frequency by multiplying, for example, the digital signal for two channels by the rotor ω. Therefore, when a digital signal for two channels is to be separated as mentioned above, the frequency shift circuit for arithmetically operating the rotor ω may be disposed for each channel to perform frequency shifting using each circuit.
However, it is desirable for the above mentioned existing frequency shift circuit to set the rotor ω highly accurately. Specifically, in the above mentioned existing frequency shift circuit, for example, if the frequency of 2.5 MHz is shifted with an error of about 0.1 Hz, the accuracy of about 25 bits will be desirable for the rotor from the following formula (1). That is, in the existing frequency shift circuit, execution of complex multiplication of 25 bits may be desirable for each sample, which may cause such a problem that the throughput is increased.Log2(2500000/0.1)=24.6  (1)
On the other hand, there exists a frequency shift circuit which is configured to solve the above mentioned problem by looking up the rotor ω from a table and not executing complex multiplication of 25 bits on each sample from several years ago. The above mentioned existing frequency shift circuit is configured to calculate only the angle with an accuracy of 25 bits and to store the rotor ω in a rotor table. The rotor needs only have the accuracy of the number of bits which is the same as that of, for example, an A/D converter and the accuracy may be set to 10 bits by way of example. In the above mentioned situation, the angle resolution will be 12 bits. That is, the above mentioned frequency shift circuit reduces the angle resolution of the angle θ which has been calculated with an accuracy of 25 bits to 12 bits and looks up a value exp(2πjθ) from a predetermined rotor table based on the above 12-bit angle information to output the 10-bit rotor ω. Owing to the above mentioned configuration, it may become possible not to perform complex multiplication of 25 bits on each sample in order to obtain the rotor ω. As a result, the throughput may be favorably reduced.
Japanese Laid-open Patent Publication No. 2000-252866 and Japanese Laid-open Patent Publication No. 7-221806 are examples of related art.